What is VHDL in Xilinx

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Why an FPGA?

When the first USB sticks with a storage capacity of 8 megabytes came onto the market in 2000, nobody really knew what storage size they would have around 15 years later in the same design. Since then, however, the requirements have changed dramatically. In the last few years in particular, storage devices, camera resolutions and the flow of data in networks have increased enormously. How are you supposed to save or even process an enormous amount of data as quickly as possible? When filming in particular, data is constantly accumulating and storage devices could only be written to insufficiently quickly, which, for example, limits recording with high-speed cameras to a few seconds.
A similar problem arose in the processing of the data. With the (relatively) easy to develop systems based on microcontrollers, the enormous amount of data in a video stream can no longer be processed in HD quality. With the emerging 4K technology in particular, even more data is being generated and the problem is worsening. In addition, it is important to bring a product onto the market in the foreseeable future in order to be able to offer a device that is not already outdated when it goes on sale.
The idea of ​​developing such a system on an FPGA (Field Programmable Gate Array) arose from the problem mentioned. The great advantage of using an FPGA is that the data can be processed in parallel instead of sequentially, which can lead to an enormous increase in the data flow. However, such a design and the programming of the FPGA is also a lot more complex and not all functions can be implemented in hardware. One of the factors that contributed to the great effort involved in such a system was that an FPGA had to be programmed almost completely in VHDL or even Verilog. Xilinx, the leading manufacturer in the field of FPGA, recognized this problem and brought a powerful tool for the development and application of systems onto the market a few years ago with the high-level synthesis (abbreviated HLS). The high-level synthesis, together with the graphic development in Vivado instead of VHDL, enables an optimized, fast development of a design without having advanced hardware or VHDL knowledge.

Why Vivado HLS?


Vivado HLS makes it possible to design IPs to be implemented on the FPGA, such as the Sobelfilter, in C, C ++ or standard C instead of VHDL. The interfaces and functions to be implemented can be developed and tested with the required high-level language. The compiler then converts the entire code into VHDL or Verilog during the synthesis. This option significantly reduces the number of lines to be written. The factor between C and VHDL code differs depending on the application and is usually in the lower two-digit range.
With the conventional VHDL design, the important timing factors had to be defined at an early stage and could only be changed later with great effort. With the capabilities of HLS, this problem has largely been resolved. In addition, together with the graphic development, HLS enables an optimized, faster development of a design instead of VHDL without having to have advanced hardware or VHDL knowledge.

Furthermore, functions of your choice can be optimized for latency, data throughput, low resource consumption, etc., this is one of the main advantages of HLS. In addition to the shorter development time, the high-level synthesis with Vivado also offers some interesting features. A design with embedded optimization instructions, so-called pragmas, can be implemented much faster and / or leaner. The application can be optimized several times and stored in various “solutions” related to the hardware, which can then be compared. This is shown below:

There is great potential for optimization, especially when it comes to filtering, which largely consists of loops.
Another advantage is that the functionality can be carried out before the synthesis. The HLS analysis function makes it possible to see how the software is running in relation to the clock frequency. Thus, for example, it can be recognized where and why the performance of the application is being limited, for example by an unexpected delay of a function. The same goes for resource usage.
The steps mentioned have become much faster and clearer thanks to the possibility of programming in a high-level language. This and the clearly designed interface are the main reasons for using Vivado HLS.