What are the limitations of the MOS transistor

Limitations of MOSFET Pair Current Mirrors

simulate this circuit - scheme created with CircuitLab

Are there any known drawbacks to simple MOSFET pair current mirrors like the NMOS version above that need to be considered? For example, the above example doesn't perfectly reflect the current (I really don't know as the LTSpice-Sim works perfectly).

I close the discussion about parameter mismatch between the MOSFET pairs (V_TO, λ, K etc) and the condition I_REF ≤ V1 / R_LOAD, but more about Noise or preload or similar.

What I mean is is this just an average as a current reflection? Just like a common drain Sorting in Average has a voltage gain of a little less than one?

TO EDIT:

What about the frequency response? Can MOSFET pair current mirrors reach the GHz range? Or is it pointless to ask? Is this the simplest MOSFET based current mirror?

Ignacio Vazquez-Abrams

It is exactly a current mirror, the ratio depending on the ratio of the lengths of the channels.

kozner

I don't need a power amplifier.

kozner

I suppose you can pretty much guarantee the L and W of a MOSFET if it's made in the same chip, but it's more difficult for different lots or manufacturers, even for the same part numbers. So I ruled out these issues as no one can do this at the design stage. Maybe I need special tools to measure and adjust everything.

kozner

"Base"? You mean "goal"? They drain through the channel (some leakage from gate to source. With very, very small signals (small currents), the high impedance across the drain-source channel allows the build-up of voltage and when charged to V_OV> 0 release much larger ones Stream through and discharge the charge at the gates, this causes the channel to stop conducting, which creates the impedance that builds up at the gate, and it keeps happening.

kozner

I am satisfied enough with the small signal model shown above, I have no problems with it. But for larger currents I really cannot deduce from the Schichman-Hodges model how the incoming original current (due to the low impedance of the already active drain source) would generate enough voltage that is exactly needed to allow the original current . From an intuitive point of view, I think that the current allowed by M1 should be less than fed in by it. Maybe I should look at the Inversion Depletion Layer Model.

Bhuvanesh Narayanan

One of the reasons could be that the right side resistance is different than the left side mirror because you have an extra load. This would therefore lead to a slight deviation in the mirrored current. Or the mosfet on the right is not saturated! Because 100mA is a lot of current and the voltage it would produce at the gate of the left mosfet would be high so Vds of the right mosfet is small compared to Vgs (since the same Vgs is given to the right mosfet) so place the right one Mosfet in the triode region. Check to see if the mosfets are saturated first. If so, the deviation is only due to differences in Vds from the two transistors.

kozner

You are probably right. If I had to choose, I would have both satiated. I haven't really figured out how to do it.

Bhuvanesh Narayanan

Here's how you can calculate your Vgs. Id = (K * W * (vgs-Vt) ^ 2) / 2 * L (saturation range formula for a Mosfet). So since you know the ID, K, W / l (if not, choose the aw / l ratio) and Vt (which should be in the datasheet for this mosfet) you only have your Vgs which are unknown and which these can now be calculated.

Autistic

M1 and M2 have DS voltages that are very different so you cannot expect your simulated current gain to be one. A cascode scheme would work better. In the 1980s I lashed some BJT current mirrors with discrete BD139 to produce 200mA. The results were terrible. Mosfets have worse spreads than BJTs. So if you build these in any quantity it would be a manufacturing disaster. Plug some min / max gate-source threshold voltages into your simulation and see for yourself. Source resistors will help, but their values ​​will be wastefully high if you want to gain unit accuracy.

kozner

So I need to find a way to create both exactly the same V_DS and in the region of saturation.

Dave

There are A Bias issue you may encounter with these. You can exceed the Vgs limits for M1. Remember you biased the drain and gate to the same voltage, where Vds = Vgs

Brian Drummond

While this can be a hypothetical problem. With an IRF530 at 100mA, I think Vds = Vgs = something pretty small.

Dave

@ BrianDrummond, I took it as a "more general" question. To be honest, I didn't think kozner would actually use IRF530 (Power Mosfets) for a 100 mA current mirror.

kozner

I missed this one completely. I actually thought I could get cheap in the early stages of the route.